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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:25:18 01/15/2010 
-- Design Name: 
-- Module Name:    Multiplexer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- General package
use work.GeneralProperties.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Multiplexer is
    Port ( 
	        InMemory    : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  InExternal  : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           InAluOut    : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);	 
           InImediate  : in  STD_LOGIC_VECTOR ((bus_size - 6) downto 0); -- 10 downto 0
           Sel         : in  MultiplexSignals;
           Y           : out  STD_LOGIC_VECTOR ((bus_size - 1) downto 0));
end Multiplexer;

architecture Behavioral of Multiplexer is

begin
  process (InMemory,InExternal,InImediate,InAluOut,Sel)
  begin
    case Sel is
	   
		when sel_Memory =>
		  Y <= InMemory;
		  
		when sel_External =>
		  Y <= InExternal;
		  
		when sel_AluOut =>
		  Y <= InAluOut;
		  
		when sel_Imediate =>
		  Y <= "00000" & InImediate;
	 end case;
  end process;

end Behavioral;

